magiczixiao

I am trying to deploy this project using pac-a10 board, and got this error during fpga_crossgen step. ``` In file included from /root/workspace/zxwang/hexl_lite/device/lib/hls/mod_ops.cpp:9: In file included from /opt/intelFPGA_pro/quartus_19.2.0b57/hld/include/HLS/ac_int.h:103: In file...

训练时validation阶段卡死

3

作者您好! 我使用CASIA数据集自行混合生成了训练和验证数据集, 可以进行训练, 但在每个epoch后的验证阶段会不定期卡死. 验证时调用的的函数为trainer\trainer.py: validation(self, epoch), 请问您是否有解决方案? 谢谢!

Automatic server restart issue when programming fpga.bit

5

When we use the JTAG programmer to download the fpga.bit file to the Alveo u50, the server will automatically restart. After restarting, the lspci will not be able to locate...

Internal error: Cannot run timing on a non-timing device

2

We are running `make` under `..../corundum/fpga/mqnic/AU50/fpga_100g`, the board package for au50 is installed and our vivado version is 2022.2, whith SW Build 3671981 on Fri Oct 14 04:59:54 MDT 2022,...