Martin Erhart

Zero width values would be very helpful from a Moore/LLHD perspective as the Moore frontend frequently emits `array_get` operations on size=1 arrays, but also other extract/slice operations requiring `i0` indices.

> Excellent. Thank you Martin. @TaoBi22 did all the work here. Just noticed that this hasn't been closed yet. Thanks Bea!

There were still a few things missing in MLIR-tablegen to generate printers from the assembly-format etc. with the new prefixes which were addressed in https://github.com/llvm/llvm-project/commit/6a99423390995f874ee4e345157523f4139ccbef We should bump the LLVM...

Dialects that have adopted prefixed accessors so far: - [ ] Calyx - [x] Comb - [ ] ESI - [x] FIRRTL - [ ] FSM - [ ] Handshake...

It's really cool to see all this progress in this direction! Can't wait to implement the first arcilator integration test using this infrastructure. I agree with @fabianschuiki that these things...

Since the `!arc.sim.instance` type will have a symbol parameter, every op with such a type will implement the symbolUser interface which can look up symbol-defining ops in `verifySymbolUses`. It works...

> The symbol use verifier can still access the op referenced by the symbol though, right? Yes, the `verifySymbolUses` function is called in the region verifier of the operation that...

> I picked up https://github.com/fabianschuiki/moore/commit/37f9596fb80fcf5fd38968fef57447d8a9082068 from your branch. Are you ok with merging that (with the addition of my fixes in [8fd4ee59](https://github.com/fabianschuiki/moore/pull/252/commits/8fd4e59be079fd2b99e302f69fb0df3339fe5dc0))? Of course, thanks for picking it up!

Sounds great to me! Just wondering whether we can use (part of) the SV dialect in the lowering chain from SV AST to HW/Comb/LLHD. And whether this would make sense...

Thank you for the detailed description! I completely agree with that. I already started with a skeleton dialect for Moore MIR, some types and three ops forming a simple example...