Michael Tempelmeier

WIP! Currently needs Verilator >= 5 and c++14. This PR is based on https://github.com/lowRISC/opentitan/pull/22230

[prim_ascon] Initial commits for the ascon primitive

3

This adds the basic structure for the ascon primitive It includes @mustafa-khairallah sbox and round function, as well as a very basic testbench.

ktp.next() for keys

3

As discussed in https://github.com/lowRISC/ot-sca/pull/115 and https://docs.google.com/document/d/1sZjASiUji_IT-t9jEFlK-kGc_Gw3mGfubNvpkM_IQT4/edit#heading=h.qd65x0y76b0e we should check the usage of `key, text = ktp.next()` in `cw/capture.py` Default behavior is that `ktp.next()` returns `const_key, random_plaintext`. This default behavior can...

[ascon] Basic testbench for TL-UL interface + hwext data register implementation.

3

rebased. This PR adds a basci testbench connected to the TL-UL interface. Currently a static sequence is sent. The response is also compared to a static sequence. If every response...

[ascon_core] add ctrl/status information

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This PR implements the following tasks from https://github.com/lowRISC/opentitan/issues/22452 - [x] add mubi signals - [x] hook up duplex FSM state register to debug register - [x] create error codes and...

### Description ### Problem If regtool is used to generate the register-documentation, for example `./util/regtool.py -d hw/ip/ascon/data/ascon.hjson > hw/ip/ascon/doc/registers.md` The markdown file ends with two empty lines. However, this is...

[ascon] Make alerts visible in the status register

4

### Description From https://github.com/lowRISC/opentitan/issues/22452 We have defined the following fields in the Ascon Status Register: https://github.com/lowRISC/opentitan/blob/0ff694a0812fe2f67da5716385bb3bc7443a9d48/hw/ip/ascon/data/ascon.hjson#L615-L651 However the information in which register the update error happened is not exposed by...