Jiajun Thomas

Hi, thanks for your great work and sharing. I encounter some problems when I compiled the mobilenet_v2_tfslim.py after initialized to tensorflow-slim submodule (git submodule update --init --recursive). And build online_model...

Errors on "make -j8"

7

make -C pkgs make[1]: Entering directory '/home/enai/Desktop/project/heterocl/pkgs' /bin/sh: 1: /home/enai/Desktop/project/heterocl: Permission denied make[2]: Entering directory '/home/enai/Desktop/project/heterocl/pkgs/cmake' /bin/sh: 1: /home/enai/Desktop/project/heterocl: Permission denied make[2]: Nothing to be done for 'all'. make[2]: Leaving...

MobileNet V2 Convertion

4

Hi, thanks for your great work on HLS art. Currently, I want to use your lib to implement the MobilnetV2 model. But some problems happened here, would you mind helping...

Hi, thanks for your great open-source works for FPGA. But currency I encounter some difficulties with your reference work. Here is few problems: 1. When I converter your three-layer of...

VGG-16 implementation based on hls4ml

1

Hi, I use your hls4ml lib to implement VGG16 on Cifar-10 dataset. The project can passed synthesis, but syn reports too many II vilation. Another problem is that cannot load...

Hi, there are some unsatisfied errors happened when I complied ur DWC kernel following this link : [https://autosa.readthedocs.io/en/latest/examples/dnn_ops.html](url) Vivado 2020.1 (Used) ``` Results show like: `****** Vivado(TM) HLS - High-Level...

Hi, I encounter this *.inc error when I try to make -j6 for ur makefile. ``` [ 40%] Built target LLVMDiff [ 40%] Built target llvm-jitlink-executor [ 40%] Building CXX...

Hi, I am researching on ur CUDA of butterfly. Sorry about my limited CUDA experiences. I read ur load_max5 function which includes remaining_input_idx, low_bits, high_bits and etc. It's not clear...