Yunkun Liao

icon indicating a website link liaoyunkun.github.io icon indicating an email [email protected]

icon company Institute of Computing Technology, Chinese Academy of Science icon location Beijing icon location | PHD Student@ICT,CAS[2020-] | | Bachelor-MicroEE@SJTU[2016-2020] | | Computer Architecture | | ASIC/FPGA Design | | RDMA | | SmartNIC/DPU |

Results 7 issues of Yunkun Liao

求prune_utils.py

10 comment

请问有人在OxfordHand数据集上得到与作者差不多的结果吗？同样使用Network-Sliminng的思路进行剪枝

1 comment

关于第一步的稀疏化训练问题

4 comment

您好，我在COCO数据上进行剪枝，目前正在跑稀疏化训练，请问停止稀疏化训练的标准是什么？

failed to modify QP to RTR for RoCEv2

Hi, your work is pretty good. I encountered "failed to modify QP to RTR" bug in my RoCEv2 environment. I found that the bug is due to the missing of...

Document Error

In this Document page https://spcl.github.io/pspin/compile/, should define VERILATOR_ROOT not the VERILATOR_HOME.

Where are the reduce and strided_ddt workload?

1 comment

Integrate silicon-proven RDMA NIC (JingZhao) into Corundum.

Recently, researchers from the Institute of Computing Technology, Chinese Academy of Sciences release the JingZhao RDMA NIC (https://github.com/ETH-PLUS/Jingzhao.git), which is open-source, full-fledged and silicon-proven (taped out successfully). Some design details...