Aidan Klein
Aidan Klein
I think I understand the problem and I'll blame myself. I added code to read the simulation time precision and adjust that into nanoseconds. The underlying simulation can have variable...
Verilog time scale would be a good start in most cases. Other cases we may need to read out the sim time scale to be sure. I can also see...
I removed the extra code in the sleep function. Xilinx sims will now sleep at the kernel time scale.
It's almost that simple. We'll need to know what sleep time unit the sim is using. I'd also like to optionally set the sim time scale with something like `.withTimeScale(fs)`...
Compile bug fixed. It took an embarrassingly long time to figure out the extra underscores were the problem.
Should sim sleeps in cycles use the time scale? Shouldn't we default to 1 ns to match older expected behavior? I'd prefer to keep time precision undefined and unforced. There's...
I also only have the open source simulators. I roughly put in time precision support for VCS. Looks like the flag was already in there.
I have tested this on XSim because it's free and I'm a Xilinx fan. :P That's actually where I first started work on it.
Yes as it is now it only supports one transaction. The original intent was to support Lite conversion. I'll give increasing the performance some thought but otherwise it's already useful.
Axi4AxUnburstified does the major work here but there's an extra step for generating R last or accumulating B resp values. I'm working on a possible solution for multiple pending transactions...