Kevin Bracey
Kevin Bracey
If no real RTOS is present, use a CortexM provider that gives us two Main and Process threads. Reworks entire thread provider system to be composable. There is always the...
This follows discussions with Alan Hayward, and research into the issue of showing HardFaults etc decently. There has been discussion and attempts to patch GDB to let it unwind from...
When installing a kernel, initramfs or device tree, also install a detached signature (.sig) file if present. Intended to support GRUB GPG signature enforcement. This does not currently lead to...
We've had a report that GCC doesn't like the MVE version of arm_biquad_cascade_df1_q15. And its complaint seems valid: https://github.com/ARM-software/CMSIS-DSP/blob/302897a523f5abae63fae9bdb3bbfc1e3089a55a/Source/FilteringFunctions/arm_biquad_cascade_df1_q15.c#L105-L108 > arm_biquad_cascade_df1_q15.c:106:13: error: incompatible types when assigning to type 'q15x8_t' {aka...
The MVE implementation of `arm_scale_q15` does not use a 2.30 intermediate, as per the documentation and other implementations, but truncates the multiplication immediately to 2.14. This reduces the output range...
The shifting copy of `mod` into `mod_multiple` would overrun the destination if the high word of `mod` was zero, so `word_shift` > `num_words`. This is not the case for any...
I just noticed the new `MPU_ATTR_NORMAL_OUTER_NON_CACHEABLE` etc defines. A few issues with these, in descending order of importance: * The `TR` transient indication is inverted. Bit 3 needs to be...
core_cm55.h and core_cm85.h have `EWIC` and `EWIC_Type` definitions, but these describe the "EWIC interrupt status access" registers in the core that provide access to the NVIC for the benefit of...
Extend unaligned access support macros to cover 64-bit accesses.
We've been running benchmarks to compare performance with other toolchains for Cortex-M55, and the compiler is performing pretty well on the actual compilation - clearly superior to GCC because of...