Pablo Mora
Pablo Mora
It would be awesome to add support for verilog language! Thanks!
just wanted to say big thank you for the perfect working and explanation!
From reading the following sections https://hledger.org/1.26/hledger.html#setting-amounts https://hledger.org/1.26/hledger.html#regular-expressions I think that a conditional %amount comparison against an integer it is not possible This is a very nice to have feature since...
Hi, hledger html help is quite detailed indeed but I think not so much reader-friendly. It is very easy to get lost with all info in a long, single-page html....
Hi, first of all let me say thanks for `hledger`. Not only for the tool itself but especially for all the documentation, very needed to us people not familiar with...
I do not think at the moment is possible to create `Seq` objects made out of combinational logic, in the same way that it is possible with sequential logic, as...
Verilog output file has two empty lines before the `module` keyword ``` ('\n' '\n' 'module blinkled #\n' '(\n' ' parameter WIDTH = 8\n' ')\n' '(\n' ' input CLK,\n' ' input...
I am using a python list comprehension to create on the fly the inputs ports for my module. `inputs = [m.Input (str(name), bw) for name,bw in ports_dict]` Where `ports_dict` is...
Documentation says > You will need some minimal Texlive distrubution I installed both the "small" and "medium scheme" from texlive 2021 installer, but in both cases I am missing some...
Hi, eager to try this tool but I can't get it to install. First of all it doesn't automatically install pycairo and pango dependencies? (hdlparse is installed fine though) Then,...