Kareem Farid
Kareem Farid
Yes. Although `DESIGN_DIR` can be used in a `config.tcl` file. But Yes I don't disagree. Let's try and narrow them down to the ones that do need documentation
I already eliminated a lot of variables but it's hard to know them all.
If you already know some that need to be eliminated from this list other than `ECO_*`, please mention them
It shouldn't as the cell are already placed. Unless that's the intention which would be weird. I will have to check anyway.
can I ask why do you need the full design ?
but the verilog isn't a factor here, as far as i know. openroad reads a def/lef and pdn commands file and these are the things that affect pdn output in...
how is this not an ideal macros to connect to? the macro has power pins and there are stripes inserted by pdn that pass through the macro's pin and pdn...
Are you trying to say that verilog parameters have no effect in blackbox modules ?
I think I understand. The thing about blackboxed macros is that, well, they are blackboxed. So I don't it is possible with the current tools at hand to have "parameterized"...
That's also a possibility.