julianstj1
julianstj1
How did you force it to override to X0Y4? I'm running into the same issue building for my design. EDIT: Nevermind, I figured it out. Added these lines to s7pciephy.py...
1. You can use different MACs , OCXOs, and TCXOs. We will release an OCXO daughter card that sits in the same footprint as the SA53 to support this soon....
Will leave this as an open known issue, for when we have some time to go back and clean up the Title block templates.
Since this is an open issue, will comment on my current view of this. We're working on enabling MSI-X in the Time Card as the primary mechanism for interrupts. I'm...
This will be a common ask from PCBWay. Yes, either way will work. I typically build with resin in all vias, but doing it only for via in pad vias...
This is on the production card, and the USB interface worked when we tested it, but definitely this double termination should not be there. If we ever have another BOM...
Hello, is there any update on this? I built custom PCBs with multiple ESP chipsets per board. But we need to capture CSI for FTM packets in order to capture...
Thanks for highlighting this issue! If I respin the OCXO board, will address this. If you want to request a merge to fix this, we can do that as well...
Great catch here as well, same comment as other issue, will fix if respin OCXO board.