Yu-Sheng Lin

Results 4 issues of Yu-Sheng Lin

Hello, I find that it can be good to be able to measure the memory latency in sysbench, similar to AIDA64 cache & memory benchmark that works on Windows. Therefore,...

I tried this on the master branch (96f9f8558bd47f8291bdd615abecb957a7004e5b). ```verilog module Top( input a [5], output logic b ); assign b = a; endmodule ``` Apparently, the assignment is incorrect and...

area: elaboration
status: ready
type: feature-IEEE

Hi developers, I have used `BOOST_HANA_DEFINE_STRUCT` in my project and find it very useful. Thanks for the great work. When I was using the library, I came up with an...

Dear author: Thank you for creating and maintaining this project. Recently, I’ve been exploring preprocessor-based arithmetic, and I’d like to propose a pull request that significantly **extends the supported range...