Johan Peltenburg

SetTracerProvider with a new NoopProvider wrapped in a type-inferred nostd::shared_ptr causes segfaults in Release builds

2

### Environment GCC 9.4.0 Compiler flags: `-O3 -DNDEBUG` (CMake Release) or `-O2 -g -DNDEBUG` (CMake RelWithDebInfo) Default CMake options, linking only to opentelemetry_trace OpenTelemetry C++ 1.4.1 ### Steps to reproduce...

AxiTop has an unused REG_WIDTH generic. This should be removed, since this width is hard coded in the generation output for the same reasons as #243 and can only be...

To prevent ambiguity between stream handshake valid, empty list (dvalid=0) and Arrows validity bit the proposal is to change: not(dvalid) -> empty null -> validity

Desired implementation to solve this could be to have a seperate MMIO register to signal there is an implicit null bitmap (e.g. all data is valid). This bit should end...

Bus address width is a generic on the top-levels, but it's not a generic for the widths of output registers for vhdmmio (understandibly). The easiest way to fix this would...

Currently the AXI top-level output of Fletchgen using --axi doesn't provide a simulation like the simulation top-level that it can generate using the --sim flag. It would be nice to...

AXI4 arlock/awlock has width of 2 bits instead of 1 bit

1

According to AXI4 spec, arlock/awlock signals should be of width 1. However, in (as far as I can tell) all sources that contain an AXI port, they are of width...

Integrate AXI protocol checkers

1

There is Xilinx IP that checks for violations of the AXI protocol on a bus: https://www.xilinx.com/products/intellectual-property/axi_protocol_checker.html When designing a HDL core through SNAP it might be useful to insert this...