memsim
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Memory Simulator and Optimizer
Currently the first word of a cache line is always loaded first. The critical word should be loaded first to allow the access to continue without waiting for the rest...
Currently the cache VHDL model assumes all ways of the cache can be accessed in a single cycle. Due to timing issues with such an approach, the simulator makes the...
The simulator should support pipelined memory accesses (multiple outstanding requests). Introducing memory banks and arbiters would be a way of doing this.
The optimizer and simulator should support stream buffers. See: Norman P Jouppi. Improving direct-mapped cache performance by the addition of a small fully-associative cache and prefetch buffers. In Proc. of...