Correct VHDL model for high-associativity caches

[joewing]

Currently the cache VHDL model assumes all ways of the cache can be accessed in a single cycle. Due to timing issues with such an approach, the simulator makes the assumption that it can take multiple cycles for caches with high associativities. Note that the superoptimizer rarely selects a high-associativity cache due to the additional cycles in the simulation model, so this has yet to be much of a problem.