Jon Klapel
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Jon Klapel
@pedronevestopic Were you able to make any progress on making the VHDL work in XSIM?
@PetterssonMagnus I was able to take the xsim branch and get it working for VHDL testbenches at a very basic level with only a day or so of tinkering with...
Has any progress been made on this issue? We are testing out Verilator and use nested classes fairly extensively in our testbench framework.