Dimitrios Andronikou
Dimitrios Andronikou
> Take a look at the .v.pyv files which produce cache RAMs and see the parameters that are being used in those. Try searching the repo on github for `MakeGenericCacheDefine`...
ok thank you very much! I will try this
I had the same problem. The problem was created after rebooting the server hosting openocd and having the fpga connected to it. The server was running openocd when I rebooted...
> I would recommend against using UART for Linux boot. It's pretty likely that there could be a data corruption over the course of loading the whole bitstream. Perhaps you...
> hi @jimaandro Yes I can use UART for linux boost but I could take a while (~10minutes). Just use your bbl (place it at openpiton/piton/verif/diag) as a prebuild image...
Hello @khoatm98 Thanks! If you are using OpenOCD, where do you copy the bbl.bin? I suppose 0x80000000 is the correct address, but this doesn't work for me. And after you...
> Hello @khoatm98 Thanks! If you are using OpenOCD, where do you copy the bbl.bin? I suppose 0x80000000 is the correct address, but this doesn't work for me. And after...
> I believe bscane2 is on the regular JTAG chain with the micro usb Hello, I have managed to connect to Debug module with jtag using openOCD. I didn't used...