Joseph Melber

Transform data on fly for larger MemTile Tiles

Trace setup and infrastructure is manually inserted into designs now, it could use some ease of use features to clean it up.

If possible, remove this [prolog](https://github.com/Xilinx/mlir-aie/blob/d960ffd5f1954538b13509b3f7f4f99c50db0073/lib/Targets/AIETargetIPU.cpp#L32-L37) from the IPU sequence.

Use GitHub pages for tutorial READMEs

4

This would improve the experience and overall flow.

* remove checks for chess mk and DSP lib * verify FindVitis works on native Ubuntu and WSL

TODO: Use `run_on_npu2` check to build on Ryzen AI targets but only run on compatible targets

[WIP] Enable build mlir-aie and run tests without Vitis

1

Discover "supported" components in Peano. Add workflow to build and run Tests and Examples without xchesscc. TODOs: - [ ] compile `aie_runtime_libs` with Peano - [ ] Bump cmake/modulesXilinx submodule...