Jett Rink

Results 9 issues of Jett Rink

Many of the schedulers use the `kernel.processes_blocked()` function to determine if the scheduler should even look at the processes to schedule them. If `processes_block` is `false`, then the schedulers assume...

### Description We want to give the option for one stage of FW (e.g. ROM) to be able to read a potential candidate for the next stage of FW (ROM_EXT),...

IP:flash_ctrl

### Description When ROM_EXT is deciding and verifying which slot of owner firmware should execute, any flash ECC error while reading the potential owner firmware image should be treated similar...

Hotlist:Security
SW:ROM
SW:ROM_EXT

If the ROM only performs a single read operation on the resistor strapping pins, then it will not be able to tell the difference between weak (e.g. 1M) and strong...

SW:ROM

### Description TLDR; The [`WAKE_INFO.REASONS`][1] register is reporting `0x00` upon every wake by any source in certain states. We are working with the [ULP wake feature on the SystemReset Controller][1]....

### Description We would like to support dual signature verification for the transition to ROM_EXT and owner firmware. This means the image manifest needs to support two signatures, one for...

SW:ROM
SW:ROM_EXT

### Description When we enabled [address_translation] in our manifest, we started to see errors, and it took a little while to figure out what was going wrong. I traced it...

prodc-integration

### Description Using the latest ROM_EXT binaries on the `earlgrey_es_sival` branch at `sw/device/silicon_creator/rom_ext/prodc/binaries/rom_ext_real_prod_signed_slot_a_fpga_cw310.signed.bin`, I get the following boot error ``` ROM:2ac41496 BFV:01525202 LCV:21084210 VER:4f70656e ``` I didn't change the bitstream...

SW:ROM_EXT

The `write_to_prefix` function is generating a panic path in our code, and I am pretty sure it is the `bytes[..size].copy_from_slice(self.as_bytes());` line. The compiler doesn't have enough information to elide the...