Jeff Setter

Add with carry operator: `a + b + 1`

Zero Latency Memory

2

The memory abstraction that I would like for simulating my circuits is a memory where the read data appears at the same time as the read address comes in. Note...

Floating point support: CoreIR and simulator

3

Add support for all floating operators: add, mul, sub le, lt, ge, gt, neq, neq, neg, sqr, flr, ceil, abs, min, max div, rem log, exp, pow, sqrt sin, cos,...

Bugs in verilog output

1

The following generated verilog has two bugs in generation: 1) VTop does not have a clk signal (line 568 of uncorrected) 2) Invalid verilog syntax (line 48 of uncorrected) [uncorrected...

The following design is intended to perform 'out(x,y) = in(x-1,y) + 3*in(x,y)'. The output values have been checked correctly for cpu (using Halide) and coreir (using the coreir interpreter). However,...

Small resnet layers segfault

1

I'm experiencing a segfault when running the unoptimized version of this resnet layer. Larger layers seem to work fine. App: https://github.com/dillonhuff/clockwork/pull/170

Boundary Cases

4

I was wondering if these outputs from Halide were valid in clockwork. And if they properly map to the FPGA (I already know that the CGRA has issues with these...

BFloat implementation

2

Several of my applications use bfloat types, including applications intended to test the bfloat hardware on the CGRA. What is the plan for supporting bfloat16_t?

Issues with dynamic stores/loads

7

I tried making a histogram test, but am having issues with the unoptimized version running. The error I encounter is: ``` bin/unoptimized_histogram.cpp: In function ‘void op_hcompute_histogram_stencil_1(bin_stencil_cache&, histogram_stencil_cache&, int, int, int,...