rohd-vf
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intel
The ROHD Verification Framework is a hardware verification framework built upon ROHD for building testbenches.
## Motivation It would be nice to offer the ability for users to add any number of arbitrary phases as needed for their project. ## Desired solution Perhaps some `Future`s...
## Motivation Many people coming to ROHD-VF will have some experience in SystemVerilog UVM. An example of how they differ would be valuable. ## Desired solution Add documentation and/or an...
### Motivation It would be nice to capture the log prints from `Test` and redirect them, e.g. to a file or some other stream for processing. Currently, it always just...
### Describe the bug If `Simulator.run` throws an exception, the `Test` should immediately end (and fail). However, as currently implemented in `start`, it can cause a hang instead. Depends on...
### Motivation When you write tests in Dart, you can use things like `expect` to ensure something is true or else fail the test. In ROHD-VF, the preferred mechanism is...
### Motivation Constructing a DUT using `Module.build` or other time-consuming functions can be nice to run prior to `run` phase. ### Desired solution Change `build` to return `Future`. ### Alternatives...