Add some example(s) on how code looks in UVM/SystemVerilog vs. ROHD-VF to help new-comers

[mkorbel1]

Motivation

Many people coming to ROHD-VF will have some experience in SystemVerilog UVM. An example of how they differ would be valuable.

Desired solution

Add documentation and/or an example with the same thing implemented in SystemVerilog/UVM and ROHD-VF.

Alternatives considered

Leave documentation solely focused on ROHD-VF.

[mkorbel1]

One key thing to include here is the difference between fork/join and Futures/await, and Streams vs. analysis ports/exports.