Mikhail Sokolov

> IO BAR space is not a thing on ARM platforms, so that's expected. Hmm, after reading this (https://github.com/geerlingguy/raspberry-pi-pcie-devices/issues/3): > PCIe interface seems happy with the default BAR space: and...

Feb 8. I spent some time thinking of the NIC development. To eliminate the risks associated with ECP5 and PCIe soft IP core I suggest this plan. 1. Buy ECP5...

Feb 12. Small update on EasyNIC. 1. ECP5 devkit with PCIe x4 is on the way to me http://www.latticesemi.com/Products/DevelopmentBoardsAndKits/ECP5PCIExpressDevKit 2. I got developer docs for Microsemi 10G PHY VSC8486, schematic...

Reading through the user guide for ECP5 IP core, the max performance of the core is 8 Gbit/s, either in x2 or x4 case. In x2 transceivers can work at...

> I wonder if a better PCIe core is available that can do 16G? I'm asking the Twitterverse. I didn't find anything. Also if we will find anything I doubt...

Having in mind restrictions and risks with ECP5 and 10G PHY, I would like to suggest an alternative way for EasyNIC. I looked for the available boards based on Xilinx...

Hi @mithro . About LiteEth, no I didn't. I definitely will look at it. Do you think it's possible to get 16 Gbps on ECP5-5G with LitePCIe?

I almost get ECP5 devkit with PCIe x4. It has LFE5UM-85 chip with 3 Gbps transceivers. I can swap the chip to LFE5UM5G-85 with 5 Gbps transceivers (they pin-to-pin compatible)....

@lukego I share you point. I looked at YosysHQ/nextpnr, they hope to get support of Xilinx 7 series with help of https://github.com/SymbiFlow/prjxray . As I said before the major problem...

My current thoughts on the topic. 1. I found a way how to deal with the 10G PHY problem. We can use 10G PHY with XAUI interface but additional ECP5...