imerkado91

Hi! Can we add a feature that will add the registers/fields names and descriptions from the RDL to the SystemVerilog files? It will make debugging the modules much easier if...

Raising an error for unauthorized read or write

6

Is it possible to add an indication for unauthorized read/write (or maybe it already exists and I missed it...) For example, let's say that a field/reg is defined as sw=w,...