hyperion009

Missing a module tc_clk_gating

1

Hi when the flow was compiling the RTL files, the following issue popped up:  It seems that there is no module tc_clk_gating after grepping the whole tree. my compilied...

mismatch between spike sim and rtl sim

2

Hi I used the RTL code of ibex-pulpissimo-v6.1.1 and kicked off the following test case: make TEST=riscv_arithmetic_basic_test ISS=spike ISA=rv32imc SEED=123 log:  out/seed-123/regr.log：  Could you give me any suggestions?...

Hi I am using https://github.com/lowRISC/lowrisc-toolchains/releases/download/20220524-1/lowrisc-toolchain-gcc-rv32imcb-20220524-1.tar.xz as my toolchain to compile riscv code and got the errors like:  these issues are caused by a lack of support for bitmanip? a...

debug test cases like riscv_debug_basic_test

1

Hi for debug tests like riscv_debug_basic_test, only rtl_sim will entry to execute the debug_rom code due to debug_req_i. and spike will not do that because no debug signal force it...

Memory address 0x0 is invalid

11

Hi My riscv core is used in a kind of specific suitation. The program's address linked by ld is to be at 0x0. However, I got following error messages: Access...

e7d4b281 & bf5ca309 in the ref's signature

1

Hi it's a first time for me to run a riscv-arch-test. I am using the sail as a reference and find there are e7d4b281 & bf5ca309 at the begin and...

where to set supported_xlen to 64

3

XLEN's default setting is 64. Where to set supported_xlen to 64? I got thi following issue: ERROR | riscv32-unknown-elf-objdump: executable not found. Please check environment setup I am intended to...

Hi the command "riscof setup --dutname=xxxx" are used to generate the neccesary env files. So, do I have a chance to set some arguments like xlen(default is 32) and ISA...

Hi It seems that the "no_load_stroe" option is not passed into member function gen_instr () like ```main_program[hart].gen_instr(.is_main_program(1), .no_branch(cfg.no_branch_jump));``` ``` seq.gen_instr(.is_main_program(0), .no_branch(cfg.no_branch_jump));``` ```sub_program[i].gen_instr(.is_main_program(0), .no_branch(cfg.no_branch_jump));``` which its' default is no_load_store =1 ,So,...

axi slave hanging

1

Hi I am adopting an axi slave as a memory in our environment, but it didn't exist and was hanging when test cases finished.