Andrey Guskov

Uninitialized tensors as buffer handles?

1

Is it possible to tell TFRT not to allocate memory for uninitialized tensors in MLIR but keep their attributes (dimensions, total size, unique `std::hash`-able instance, etc.)? The device I\`m writing...

ResNet50 test does not verify the result

10

Seems like the only check the ResNet50 test has is this one: ```// CHECK: int1 = 1``` How should I amend it so that it could actually verify TFRT for...

[PoC, do not merge] src: gpu: intel: add user-supplied precomputed zps to gemm

2

This is a proof-of-concept implementation of user ZPs in GEMM — ref-only as of now, and with no foolproofing. The RFC for this change [is here](https://github.com/uxlfoundation/oneDNN/pull/3136).

src: gpu: intel: remove gen9-gen11 code as obsolete

4

This resolves [MFDNN-13645](https://jira.devtools.intel.com/browse/MFDNN-13645).

This is the first part of [MFDNN-13796](https://jira.devtools.intel.com/browse/MFDNN-13796), applicable to both Conv and GEMM.

rfcs: add external precomputed zero points for gemm

1

This is a proposal for user-supplied precomputed zero points, primarily intended for boosting GEMM performance in LLMs. @dzarukin, @mgouicem, @vpirogov, please review. Related JIRAs: [MFDNN-12757](https://jira.devtools.intel.com/browse/MFDNN-12757), [MFDNN-13500](https://jira.devtools.intel.com/browse/MFDNN-13500)

src: gpu: intel: jit: clarify the naming for kernel/thread grids

1

This PR resolves the kernel / threadgroup terminological mixup in the jit:ir generator.

src: gpu: intel: concat: fix write=1, adjust for internal type size

2

This addresses [MFDNN-14306](https://jira.devtools.intel.com/browse/MFDNN-14306).

src: gpu: intel: jit: codegen: read suppression WA for fused-EU HW

2

This addresses [MFDNN-14208](https://jira.devtools.intel.com/browse/MFDNN-14208).