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                                            Henri Heimann

System clock of 32 MHz via PLLMul::Mul4 and PLLDiv::Div2 leads to hard fault because of default voltage range

When using the following configuration for a 32 MHz system clock, which is possible since #129, a hard fault is generated: ```rust let mut rcc = dp.RCC.freeze(Config::pll(PLLSource::HSI16, PLLMul::Mul4, PLLDiv::Div2)); ```...