hecmay
hecmay
This PR aims to enhance `.systolic()` and `.to()` primitive to better support intra-kernel data placement for systolic array generation using AutoSA backend. `.systolic()` primitive is a push-button API that maps...
- [x] Installation guide (e.g., docker, conda, and special instructions for Mac users) - [x] Tutorials for HCL platform, device and data movement - [x] Tutorial for HLS IP integration....
The HLS code generated for LetNet5 example can pass HLS, but it failed block-level synthesis in vpl with AWS F1 VU9P FPGA target. Here is the error message (not enough...
Im trying to reproduce some performance numbers mentioned in HCL paper on AWS F1. ```shell ===>The following messages were generated while performing high-level synthesis for kernel: default_function Log file: /heterocl/samples/smith_waterman/aws/_x.hw.xilinx_aws-vu9p-f1_shell-v04261818_201920_2/kernel/default_function/vitis_hls.log...
This is the error mentioned by Mira. The error actually comes from the old TVM part, and it complains that the placeholder op is not found in the stage_map... This...
In the prototyping, we created a naive graph partition algorithm to separate the DFG into host scope and device scope. The naive algorithm only supports generating a single kernel function,...
Current status of IP integration feature in HCL: * Support HLS IP for AOCL and Vitis flow (tested with AOC18 and Vitis 2019.2) * Support RTL IP for AOCL flow...
Here is a simplified example of HLS code generated from our 1d CONV test case ( after using .to() to customize the dataflow architecture): ```c++ void main(int*A, int*B) { for...
We need some pass to optimize the memory access automatically. Examples: * Pack multiple low bitwidth IO ports into a single IO port to better utilize the BW * Automatic...