gyurco

There is no scaler on MiST, so no need for any setting. Just choose Pentagon timings for this demo.

Probably garbage left in RAM. Try to hold SPACE while resetting the Speccy to reinitialize ESXDOS.

It works for me. If you hold space, and then press reset, then it won't work. Just press reset, then press space, hold it, and release reset.

The firmware nothing to do with this (I hope you used the core reset, not the ARM reset button). ESXDOS works this way - holding SPACE when booting will reinitialize...

If the PIC is needed, then it's out of question. If it's only needed for the extra MIDI ports, then maybe. But you won't get the 4 extra ports.

Hi! I reflect here to your mail. It would be good of course, but I don't see how can be done. For example, regressions in some 8-bit computer cores is...

About shared modules I have a principle which I first encountered in another project: don't make a module shared until 3 different systems can use it. Then if it's good...

> If the FPGA platform (the firmware) supports some way of remote control from a PC, to start a core and transfer files, then the rest of the regression setup...

As I see most problematic are the pins which couldn't be put to fast output regs. Also I wonder if a new set of PLLs should be created for the...

For the record, PLL locations in Cyclone 10: https://www.intel.com/content/www/us/en/docs/programmable/683777/current/gclk-network-clock-source-generation.html External clock outputs: https://www.intel.com/content/www/us/en/docs/programmable/683777/current/external-clock-outputs.html The SiDi128 board is designed in a way that PLL2_CLKOUTp pin is SDRAM_CLK and PLL4_CLKOUTp is SDRAM2_CLK.