gyh1997127

Results 2 issues of gyh1997127

Hi, Can someone provide more details on the synthesis data shown? i.e. did the synthesis run include FP register file, instruction decode/issue logic? Much appreciated! > Fpu 32 bits ->...

Hi, I'm noticing that the syntax folding on works on some of my files. Can you please advise how to go about debugging this? Example: ![image](https://github.com/vhda/verilog_systemverilog.vim/assets/41491404/4c133f2f-cbee-4d99-b1e5-9e3541443782) ![image](https://github.com/vhda/verilog_systemverilog.vim/assets/41491404/efd903dd-e35a-4ebf-a302-9a51b6c9749d) Apologies for not...