Gus Workman

Thanks for the quick response! I went for option 1 here, since that made more sense for my model, but it would be helpful for others who come across this...

@simon-tse-hs yeah, here is a picture.  Also, I would love to contribute to this, but I'm fairly new to programming (I'm a college student now). If you have some...

Thanks, @josevalim! I would love to help with this issue if given a pointer in the right direction!

Oh interesting - I hadn't seen the need to call `stop_dma` before. This works to fix my consecutive writes (which I didn't even realize were having a DMA issue until...

Oh and I also added the `spi.stop_dma` call in the interrupt handler, but that function is not even called so something isn't right to begin with...

Yes so in this case, I don't care about the SPI transfer data. I'm actually dealing with an SSI encoder, and given a clock it will output valid data on...

would it be possible to do something like this? ```rust self.spi.transfer_dma( &[], &mut BUFFER, // size 8 DmaChannel::C3, DmaChannel::C2, ChannelCfg::default(), ChannelCfg::default(), DmaPeriph::Dma1, ) ``` I think I tried this but...

Thanks for confirmation on that. Is there a set of registers you recommend poking around in? And I noticed there is a `dma.cfg_channel` which is public, should I be looking...

Here's another mind-boggling one: I set up the DMA SPI write such that it will trigger when complete to unset the chip select. ```rust #[interrupt] fn DMA1_CH5() { dma::clear_interrupt( DmaPeriph::Dma1,...

The main buffer I'm trying to read into is already static - ```rust pub static mut BUFFER: [u8;8] = [0; 8]; self.spi.read_dma( &mut BUFFER, DmaChannel::C2, ChannelCfg::default(), DmaPeriph::Dma1, ) ``` I...