Ganesh Gore

Why deprecate the `Directlist` its useful in general right ?

Hello @mattvlsi `ql_memory_bank` protocol used latches instead of flip-flops. Definitely, there is an area benefit but it depends on how the latch cell is implemented in the standard cell library....

LGTM, these features are not tested on CI. @tangxifan You can merge if everything is good.

Ok, I need to update the documentation based on your PR+ additional syntax. I will do it soon and rebase

Yes, you are right, those variables are scripts internal, not system variables, so $HOME will not be replaced. The supported variables are documented [here](https://github.com/lnis-uofu/OpenFPGA/blob/1ce94040da38215aef890d0401347758fb8945f8/openfpga_flow/scripts/run_fpga_task.py#L207). While creating an independent task (not...

yeah edited the message. The documentation of all such features is lagging because of our recent restructuring and development. I will try to get all this in documentation asap.

Hello AyaseErii, You need to perform hierarchical floorplanning to achieve a tileable layout as detailed in the 20x20 FPGA layout. The OpenFPGA-generated Verilog netlist is already hierarchical, which saves you...

@yunuseryilmaz18 We have not developed a complete place end route scripts using any opensource tools like openlane or openroad. We mainly use ICC-II to perform all the place and route....

@AyaseErii The fpga_top generated using OpenFPGA has been rename to fpga_core during restructuring, and new fpga_top is just one to one mapping to the fpga_core. We are in process of...

PNG is broken in Windows 10. The saved file is 0Byte, SVG worked fine.