Frédéric Druppel

Unfortunately I'm only a team of one 😅 I'm learning FreeRTOS in my free time (which due to my studies I have not a lot of x) ), so maybe...

Created [Pull request](https://github.com/jeroenheijmans/advent-of-code-charts/pull/75) #75 for Xcode source files & Safari macOS app

Hi @jeroenheijmans Thanks for checking out the PR :) I completely understand that the way I added the code is not optimal; I did it this way so other people...

How is it possible to force pin 6 to stay the nRST pin on SOP-8 Packages ? Even if I do,'t use the pin as a GPIO, I have to...

Found a way to tell the J-Link to force-reset the chip : add ```r0``` at the top of ```/Misc/jlink-command``` file ```txt r0 erase loadfile Build/app.hex 0 noreset reset exit ```

Yes, Running on Apple Silicon. `yosys -m ghdl` works for FPGA synthesis (with ICE40 toolchains, and oss-cad-suite) but doesn't in the nix-shell for VLSI synthesis. After running `nix develop .#devShells.x86_64-darwin.default`...

All right, thanks ! I wasn't able to build the oss-cad-suite from source, so I used the [latest `darwin-arm64` build from the YosysHQ repo](https://github.com/YosysHQ/oss-cad-suite-build/releases/tag/2025-02-20).

Thanks for your reply ! (I didn't see the previous one 🤦) I'm trying to build the newest release, but I get the following error : ```zsh  8:46:19 ~/Downloads/xnec2c...