Michael Wong
Michael Wong
[CPPCON 2021 class SYCL 2020 and Futures.pdf](https://github.com/codeplaysoftware/syclacademy/files/7469460/CPPCON.2021.class.SYCL.2020.and.Futures.pdf [CPPCON 2021 class SYCL 2020 and Futures.pptx](https://github.com/codeplaysoftware/syclacademy/files/7469462/CPPCON.2021.class.SYCL.2020.and.Futures.pptx) )
As I am reviewing the slides this weekend, and they look great, the integration from other teams really added value and new perspectives. One thought occurred to me. Is there...
The closing slide is a Call to help improve SYCL. This information is already here on slide 6 which I will use in the closing section: https://docs.google.com/presentation/d/1pfQcaAEeInco9vJAV7_rnyDDea3a72pQ6VJTygkLizE/edit#slide=id.gd633468d3b_0_52
I like this section. Many images are using Figure 15-x, even though this is Lecture 14a. Probably change it so its Lecture number agnostic as we could be moving this...
Title say: Think of as a Reconfiguration Custom Chip Probably missing FPGA
We should update the implementation support list on slide 10 file:///C:/Users/michael/Downloads/syclacademy-main/syclacademy-main/Lesson_Materials/Lecture_01_What_is_SYCL/index.html Slide 5 here shows my updated picture, you can reuse: https://docs.google.com/presentation/d/1pfQcaAEeInco9vJAV7_rnyDDea3a72pQ6VJTygkLizE/edit#slide=id.gf4c98a3889_0_0
May be intentional but they are the same/ https://github.com/codeplaysoftware/syclacademy/tree/main/Lesson_Materials/Lecture_00A_Why_Parallel_and_Heterogeneous