Enrico Zelioli
Enrico Zelioli
Already included into #170.
The bootrom SMP support consists of pausing all secondary cores after a first common reset sequence, and let the main core do the initialization process. The main (non-SMP) core is...
The SMP support in the software runtime (crt0.S) instead fixes the main core to core 0. All other cores are paused after some common required initialization steps in the [crt0.S](https://github.com/pulp-platform/cheshire/blob/ez/litmus/sw/lib/crt0.S#L94)....
Zero-stage bootloader also required some adaptations wrt #85 due to the different behavior upon resuming secondary harts in the Cheshire runtime (crt0.S). When calling `smp_resume` the secondary harts jump to...
Regarding CI: > LGTM. Can we add `smp_hello` to the Cheshire CI? I remember that we previously had issues with executing from either DRAM or SPM because of the way...
> LGTM. I suggest to add this elaboration step to the CI, and to parse the generated reports for (i) Errors, (ii) Inferred latches, (iii) Timing loops. The latter most...