esynr3z
Hello, It seems that Verilator ignores `some_map_t` specialization of class `wrapper` and try to cast `this.map` to a default type. This can be connected to #4997, as I become able...
Hello, I'm getting internal error on the code below. Here I wanted to use constant string within array assignment. It seems legal and works in major simulators. The code: ```verilog...
Hi! I'm getting error when try to implement extern function that returns parametrized class: ``` %Error: test.sv:12:5: Assign RHS expects a CLASSREFDTYPE 'value_cls', got CLASSREFDTYPE 'value_cls__Tz1' : ... note: In...
Hello, I have class with some default `parameter type` and cannot override it, which should be legal. The code: ```verilog module test; typedef enum { FOO_0, FOO_1 } foo_e; typedef...
Just splitting #62 into separate tasks
It would be nice to have a way to override configuration parameters via CLI. This facilitates scripting and experimenting around tool without modifying the configuration file. It is quite a...
Some work is already done here #11 . Need to review and adapt to latest master at the moment
Single source is used for any HDL generation, but Verilog and VHDL modules stored as different jinja templates. This is quite error prone, because always during any fix/enhancement both types...
I simply like how it is organized https://keepachangelog.com/en/1.1.0/
Some advanced features require configuraion file to be more flexible and original csrconfig INI-like might be not easy to support them. That's why I want to switch to TOML. It...