Eric Su
Sure. I'll do this.
Same here !! I downgraded the operation version to resolve this issue when creating the ONNX model. I used `model.opset_import[0].version = 13`. Note that model is the result of using...
> Very exciting! Has any testing been done on real RISCV64 RVV 1.0 hardware? For testing, we have only tested the code using QEMU and the Spike simulator without real...
> when will we not have to specify `-mrvv-vector-bits`? The reason for specifying `-mrvv-vector-bits` is due to the limitation that RVV types cannot be included in Neon global structs. For...
> What's the plan for GCC support? For supporting GCC, we plan to find a flag that enables the use of fixed-length RVV types, similar to `-mrvv-vector-bits` in LLVM.
> Can you add some text to the `README.md` about using SIMDe on RISC-V? Sure !
> What about portable binaries, when will we not have to specify `-mrvv-vector-bits`? Creating portable binaries for RVV (RISC-V Vector Extension) is not feasible, as explained in the discussion at...
> @camel-cdr Thanks! > > Yeah, I'm now also seeing those errors. > > I wonder why the qemu setup in this PR isn't reproducing them? > > I hope...
I have modified mul_lane and mulx_lane. Hope the error in fms_lane, fma_lane, mul_lane, and mulx_lane will be eliminated.