Douglas Reis
Douglas Reis
I Installed the `ykman` with `sudo apt install yubikey-manager` in a Ubuntu 20.04 and noticed that the command to change the pin retry attempts has chaged. This PR updates the...
It seems that reading entropy via rv_core_ibex is slower o silicon than on the FPGA. @vogelpi
Remove the suffix `chip_` from ip_block name on testplans for consistency
### Hierarchy of regression failure Chip Level ### Failure Description 1.chip_tap_straps_rma.21772234691385209619682590200792454597286593434541981490850684438544754226470 Line 5955, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_tap_straps_rma/latest/run.log UVM_FATAL @ 60000.000000 us: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 60000.000000 us hit, indicating a...
### Hierarchy of regression failure Block level ### Failure Description UVM_FATAL @ 42408749 ps: (csr_utils_pkg.sv:594) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=0xd2d38114, Comparison=CompareOpEq, exp_data=0x1, call_count=3) UVM_INFO @ 42408749 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM...
### Hierarchy of regression failure Chip Level ### Failure Description ``` `UVM_FATAL @ * us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"` has 1 failures: *...
### Hierarchy of regression failure Chip Level ### Failure Description ``` Loading: 0 packages loaded WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/tests/autogen/top_darjeeling:plic_all_irqs_test_sim_dv': no such package 'sw/device/tests/autogen/top_darjeeling': BUILD file not...
### Hierarchy of regression failure Chip Level ### Failure Description ``` * `UVM_ERROR @ * us: (chip_sw_soc_proxy_external_alerts_vseq.sv:74) [chip_sw_soc_proxy_external_alerts_vseq] Check failed alert_rsp == alert_req (* [*] vs * [*]) Alert response...
### Hierarchy of regression failure Chip Level ### Failure Description ``` * Test chip_sw_example_manufacturer has 1 failures. * 0.chip_sw_example_manufacturer.1\ Log /home/doreis/git/opentitan.git/master/scratch/master/chip_darjeeling_asic-sim-xcelium/0.chip_sw_example_manufacturer/latest/run.log Analyzing: target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv (0 packages loaded, 0 targets configured)...