Elam Day-Friedland

`LOADMEM=` on non-LOADMEM-Capable Memory Models is Silently Ignored

1

### Background Work - [X] Yes, I searched the [mailing list](https://groups.google.com/forum/#!forum/chipyard) - [X] Yes, I searched [prior issues](https://github.com/ucb-bar/chipyard/issues) - [X] Yes, I searched the [documentation](https://chipyard.readthedocs.io/) ### Chipyard Version and Hash...

Add lumerical CHARGE integration

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**Is your feature request related to a problem? Please describe.** Being able to end-to-end simulate active electronic-photonic devices designed in GDSFactory (such as PN phase shifters) in lumerical would be...

[fud2] Synchronous Guarded Assignment Check on Combinational Component

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I have a couple of guarded assignments ``` WBSel = eq_load.out ? 2'b00; // Loads WBSel = (eq_jal.out | eq_jalr.out) ? 2'b10; // jal, jalr WBSel = !(eq_jal.out | eq_jalr.out)...

[primitives] `std_bit_slice` semantics

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(Feel free to reassign this, not sure which tag is suitable) I was trying to invoke verilator manually on a calyx-generated verilog file and got some warnings of the format...

add assert primitive and basic test

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TODO: get it working with runt. When I invoke the test with `fud` it (correctly) fails, but runt seems to complain that the primitive doesn't exist (perhaps for fud2 they...