Ekansh Bansal

[email protected]

CDAC-ACTS Pune Pursuing a PG Diploma in VLSI Design from CDAC Pune; completed a B.Tech in Electronics and Communication from GLA University. Skilled in DSD & teamwork

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                                            Ekansh Bansal

100DaysofRTL

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"100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado

ekb0412

asic

digital-system-design

fpga

verilog-hdl