edwardcwang
edwardcwang
@zhuanhao-wu In the short run, there's the option of writing a specific helper function for your usecase.
See #60. In general, translating arbitrary Scala code, which is what a testers2 program is, to Verilog is not really feasible or desirable.
If we can support Hammer simulation as a backend that would also be great...
Hammer has a simulation API/abstraction that allows a number of different simulator backends to be driven, such as VCS, ncsim, etc.
I think one possible motivation for avoiding `step()`, is that in a design with multiple clocks, it creates an ambiguity as to which clock to step.
Yeah, that's the tricky part methinks... Zero-width signals do indeed disappear in low-FIRRTL. I guess this is the inverse of #2.
Well, zero-width wires are also a Chisel/Chirrtl thing and don't actually exist in hardware...
The short-term problem which I ran into is the case of writing a test library. I wanted a way to present a friendlier message to the user about some more...
I'm fine with using named timescopes; then, is there a way to get the extra information out of it? It would make test libraries more pleasant to use if test...