David Randolph

I am having problems using Yosys in your workflow. I linked in the circuit_synthesis/lib/asic_cell_yosys_extended.lib file and removed all of the /^\s*\(\*/ comment lines in the synthesized (netlist) output. (These steps...

It would really help to have the original Verilog files used to synthesize the provided netlists. This would allow users to experience the end-to-end workflow more easily.

SCD documentation is incorrect

2

The SCD documentation says there are seven values in the first line of the flag. But all of the included files have 10 values. The code names these values in...

schema.yml says this: ``` version: 2 models: - name: CAB_ENC_MAPPING columns: - name: EncounterKey quote: true tests: - dbt_constraints.primary_key - name: ENCOUNTER_NUM tests: - dbt_constraints.unique_key - name: CAB_PAT_MAPPING columns: -...

Improve SQL Server Incremental Statement

6

## Issue Description I am incrementally slinging data to a large Oracle table via sqlldr from SQL Server. Here is an example command: ``` sling run --src-conn CDW_MSSQL --src-stream dbo.BillingTransactionFact...