duanjiulon
duanjiulon
for example,CMD runMain naxriscv.platform.LitexGen --netlist-name MyNaxRiscvLitex --netlist-directory=/home/jlduan/work1/pythondata-cpu-naxriscv/pythondata_cpu_naxriscv/verilog --reset-vector=0 --xlen=32 --memory-region=0,65536,rw,p --with-jtag-tap --with-debug --scala-file=/home/jlduan/work1/pythondata-cpu-naxriscv/pythondata_cpu_naxriscv/verilog/configs/gen.scala is also the problem, please help me ,thanks
> I would say, the best there would to not use the litex related port, but instead going with raw NaxRiscv and implementing the bridge from the native NaxRiscv interfaces....
> --memory-region=2147483648,131072,io,p => Allowed to access address [2147483648,2147483648+131072] on pBus for io access only (meaning slow, in order, load+store, can't fetch instruction from there) --memory-region=0,131072,rxc,p => address [0, 0 +...
Hi, in other words, it means that I use jtag debugging and GDB to perform read and write operations inside the core. For example, the command mww 0x40000000 0x12345678 32...
> Yes, that is by design. Hi, I have successfully read and written DDR with your help, but I would like to run a dryone through DDR and print it...
> the important things are --scala-args='rvc=true,rvf=true,rvd=true,alu-count=2,decode-count=2' Ahhhh, thank for your reply Why do ALU units need two? What I mean is, do the four parameters of the memory unit need...
> One io,p for peripherals via pbus One rwxc,m for high performance memory access and execution via mbus that's the minimum required i think hi,dear Dolu,I'm planning to use litex+nax...
No,No,No,It's not about the dhrystone program for litex, but the dhrystone program and makefile in the ext/Maxsofware directory of your Naxriscv directory， 发自我的iPhone ------------------ Original ------------------ From: Dolu1990 ***@***.***> Date:...
> No software from ext/NaxSoftware is designed to run on litex (excepted the instruction for debian) OK,fine,dear dolu,I have done this by litex intergration, But his coremark performance is around...
> I didn't tested on litex specificaly, that coremark was for simulation only. Hi，dear Dolu， 1. I would like to ask for some ideas about FetchCachePluginAXI4. scala here. Why is...