Darryl Miles

GHA skip-checks:true recomendation and behaviour not consistent with git-commit --trailer behaviour

2

### Code of Conduct - [X] I have read and agree to the GitHub Docs project's [Code of Conduct](https://github.com/github/docs/blob/main/CODE_OF_CONDUCT.md) ### What article on docs.github.com is affected? https://github.com/github/docs/blob/main/content/actions/managing-workflow-runs/skipping-workflow-runs.md?plain=1#L29 This concern the...

## Describe what is wrong or missing The tool `verible-verilog-kythe-kzip-writer` has an command line argument `--filelist_path` which expects the value to be a regular file. The file contains the contents...

It is not clear what bytecode level feature is being utilised to require JRE11 at runtime, or if this was just the release engineering JDK used on the day of...

joe: Joe's own editor

8

My first MSYS2 package contribution.

Plugin 2024 Q1 maintenance update (115 commits)

1

Update on https://github.com/unbroken-dome/gradle-xjc-plugin/pull/47 As per my comment https://github.com/unbroken-dome/gradle-xjc-plugin/pull/47#issuecomment-1848797444 this is a reopened using a separate source branch at the origin repo. Main features: * JDK21 and Gradle 8.5 tested *...

CatalogsWithCleanIntegrationTest: Failing test on Windows

1

This IT serves to document the problem. When building a project using this gradle plugin in an IDE on windows it is necessary restart the gradle daemon process (causing it...

Section for `How SpinalHDL simulates the hardware with Xilinx XSim backend` is missing.

Sequential logic/memory: matters arising from docs with annotations/blackbox/memory/device complexities

2

This started as a comment to Tranche 3 but requires more investigation to help clarify both the code/mechanisms and the documentation around it. So to track I open this. ---...

Introduction/A simple example: updated (REVIEW/ADD DETAIL)

2

Browsable preview at: https://dlmiles.github.io/SpinalDoc-RTD/docs_multi/html/vTEST/index.html https://dlmiles.github.io/SpinalDoc-RTD/docs_multi/html/vTEST/SpinalHDL/Introduction/A%20simple%20example.html# See review marker looking for assistance to reword this area. Thanks

Please Review: SPI DO OENb signal source

3

https://github.com/efabless/caravel_mgmt_soc_litex/blob/43d0ce33d331ee73d9dcebe197c6ce4da5909ecc/verilog/rtl/mgmt_core.v#L1774C31-L1774C31 This like appears to connect the SPI master controller `Data Out Output Enable (active low)` to the **INVERTED** signal of the `SPI CS (active low)` as a signal source....