dillonhuff
dillonhuff
@David-Durst I don't know why the passes that prepare the coreir circuit take a long time, though @rdaly525 may have some more insight on that. As for the performance of...
@jeffsetter good to know. @rdaly525 is there anyone else who needs it or can we remove it?
@jeffsetter thanks for letting me know. I'll leave the tests in.
I think the thinking was that we would replace the CoreIR C++ backend with just compiling to Verilog and running Verilator. I didn't realize that anyone was still using the...
@jeffsetter @rdaly525 sorry for the confusion. This question was *NOT* supposed to be about the coreir interpreter. It was supposed to be about the coreir -> c++ backend that I...
@jeffsetter I also agree that the coreir interpreter is probably not a good long term solution. Actually I've been thinking of some other ways we could do simulation that might...
Cool. I assume bfloat and 32 bit are sufficient for now?
Loading the kernels as inputs would make the array that holds the values of the kernels visible to the scheduler (which is important for reduction) and would get around this...
@jeffsetter thanks! I pulled and now I get an error finding compute units: ```bash cmd: g++ -fstack-protector-all -std=c++11 regression_tb_unoptimized_harris_sch3_1pp9c.cpp unoptimized_harris_sch3_1pp9c.cpp ERROR: Could not find Module in namespace! Module: hcompute_kernel_x_stencil_1 Namespace:...
@jeffsetter if it is easier for you in codegen another solution would be to break up compute units that read from ROMs into two statements: one statement that reads from...