Lowie Deferme

**Icon Type** - [ ] Folder - [x] File **File Names** - .ld - .lds **Graphic ideas** https://materialdesignicons.com/icon/link-variant https://materialdesignicons.com/icon/link **Additional context** A "link" icon for GNU ld linker scripts

In the current [`README.md`](https://github.com/riscv-software-src/riscv-tests/blob/master/README.md), I found the following table of all existing TVMs. However, when checking the described [`riscv_test.h`](https://github.com/riscv/riscv-test-env/blob/4fabfb4e0d3eacc1dc791da70e342e4b68ea7e46/p/riscv_test.h), I found a different set. This set is listed in the...

[Wip] Hypervisor extension support

4

I am working on support for the RISC-V hypervisor extension. However it is still very much a work in progress. The main goal of this pull request is to welcome...

According to the priv. spec. `mtime` should be readable & writable: > Platforms provide a real-time counter, exposed as a memory-mapped machine-mode read-write register, `mtime`. However, the model currently does...

Since (most) MMIO devices are not part of the RISC-V specification and are only implemented to support the emulator, it might make sense to implement them in the C emulator...

Partial PMP match reports original address in tval

2

From the priv. spec.: > If mtval is written with a nonzero value when a misaligned load or store causes an access-fault or page-fault exception, then mtval will contain the...

Hypervisor extension

2

This is a version of the hypervisor extension ported on a more recent version of the model. Feel welcome to provide any feedback In order to verify the modifications &...

Use of ext_* read/wrtite hooks for standard extensions

2

Question about [CODE_STYLE.md](https://github.com/riscv/sail-riscv/blob/master/CODE_STYLE.md): At the bottom it states that `ext*` types and hooks should not be used for standard extensions. However, [ExtendingGuide.md](https://github.com/riscv/sail-riscv/blob/master/doc/ExtendingGuide.md) claims that "access to newly added CSRs can...

The test `hs hlvxwu on vs-level non-exec page leads to lpf` fails on [`riscv-isa-sim`](https://github.com/riscv-software-src/riscv-isa-sim) (spike) because spike sets `mstatus.GVA` whereas the test [expects `GVA` to be zero](https://github.com/josecm/riscv-hyp-tests/blob/4230c9338fe1cfe37dc8ca2c5783e894fb2bcdfd/translation_tests.c#L295). However, this behavior...

### I have searched through the issues and didn't find my problem. - [X] Confirm ### About the icon A broadly used x86 assembler ### Links and sources ...