Naoya Hatta
Naoya Hatta
```systemverilog parameter logic ENABLE_FUNC_A = 1; parameter veryl_boolean ENABLE_FUNC_A = VERYL_TRUE; ``` For me, the first example is explicit sufficientlly, and the second is bit redundant. (Addisionally, identification between `VERYL_TRUE`...
I agree to introduce `true` and `false` because they show it is boolean value more clearly than `1'b0` and `1'b1`. About `bool` type, I have some concerns. `bool` type is...
OK. I understood that `bool` is a type alias of `logic` to express boolean value. I'll merge #1389.
It looks good. There are some syntax ideas. * assignment ``` modport slave = converse(master); ``` This may be diverged from the original `modport` declaration. * Rust style derive ```...
I'm working on this issue.
Feature seems to be good, but the syntax is required to consider. (`{}` is confusable with concatenation)
The same syntax with SV will conflict when the SV's feature is added in future. So I think it it better that different feature has different syntax. I'll consider another...
For example, `inplace` expression. Otherwise, `overwrite`, `replace` may be used as keyword. ``` masked_address = inplace address ([1:0]: 0, [3:2]: 2'h3); ```
> 3. Set the number of backticks based on the contents of the code block (needs elaboration) I'm interesting in this approach. In https://github.com/google/mdbook-i18n-helpers/pull/129, I wrote the following code to...
> The way I understand this is that the count of backticks depends on the nesting level of code blocks? If so, the proposed code also wouldn't reproduce the exact...