Colin Marquardt
Colin Marquardt
Synopsys VCS-MX supports not only (System)Verilog as is the case with the backend right now but also VHDL, allowing mixed-language simulation. Some pointers: - http://www.vlsiip.com/vcs/ - http://salinasv.blogspot.com/2011/05/simulating-mixed-language-hdl-using-vcs.html - https://github.com/benreynwar/vunit/blob/vcsmx_interface/vunit/vcsmx_interface.py -...
It would be interesting to see how this implementation fares with https://github.com/nst/JSONTestSuite (see http://seriot.ch/parsing_json.html).
Using current `master` (verible-v0.0-1959-gd9b88c73). **Test case** ```systemverilog $realtime/1.0e-9s ``` **Actual output** ``` syntax error, rejected "s" (syntax-error). ``` It works with ```systemverilog $realtime/0.000000001s ```
Using current `master` (verible-v0.0-1959-gd9b88c73). **Test case** ```systemverilog #0step; ``` **Actual output** ``` lexical error, rejected "0step" (syntax-error). ```
Using current `master` (verible-v0.0-1959-gd9b88c73). **Test case** ```systemverilog module stop_time; initial begin #100.0us; $stop; end endmodule ``` **Actual output** ``` tree_unwrapper.cc:2052] Formatting of macro call failed: paren_group not found. *** Please...
The ``envml`` tool that ends up in ``Modules/bin/`` seems quite useful but does not show up in the documentation (apart from the Release Notes: https://modules.readthedocs.io/en/latest/NEWS.html?highlight=envml).
A "TODO" block is near the top, with a few other TODOs further below.
Right now, we are using a two-step setup for Synopsys VCS which according to http://www.vlsiip.com/vcs/ is limited to Verilog only. VCS(-MX) is capable of simulating VHDL too with a three-step...
Our simulator makefiles get the list of Verilog and VHDL sources in separate variables, and in ``Makefile.questa``, ``Makefile.aldec``, ``Makefile.activehdl``, there are separate compiler calls to compile Verilog and VHDL. Right...
We should use our new logo on https://docs.cocotb.org/.