Chris Lavin
Chris Lavin
- Allows the random SEED to be set from the command line - Allows for return code 1 in evRouter (still generated valid solution in this case)
#477 has a workaround by adding an overload to place ModuleInst objects without allowing overlapping placement. This should probably be the default behavior. However, the `BlockPlacer2` and other code has...
One of our CI regression tests keeps running out of memory. ``` Caused by: java.lang.OutOfMemoryError: Java heap space at java.base/java.util.HashSet.(HashSet.java:106) at com.xilinx.rapidwright.rwroute.RWRoute.checkPIPsUsage(RWRoute.java:1181) at com.xilinx.rapidwright.rwroute.RWRoute.setPIPsOfNets(RWRoute.java:1170) at com.xilinx.rapidwright.rwroute.RWRoute.route(RWRoute.java:673) at com.xilinx.rapidwright.rwroute.RWRoute.routeDesign(RWRoute.java:1776) at com.xilinx.rapidwright.rwroute.RWRoute.routeDesign(RWRoute.java:1750)...
This is an attempt to resolve incorrect resolution of a hierarchical name search of a netlist object that happens to use a hierarchy separator (`/`) in its name AND also...
See discussion in #351
When Vivado reads a netlist (EDIF file, for example) it will expand the macros in it before returning control to the user. RapidWright emulates this behavior by expanding upon read...
Using a combination of #385 and `DesignTools.copyImplementation()`, it should be possible to provide the equivalent of Vivado's `write_checkpoint -cell`.
~~One useful capability would be to automatically add a buffer cell (LUT1 or FDRE) similar to the way "update_design -buffer_ports" operates in Vivado. This would help with integrating multiple designs...
One useful capability would be to automatically add a buffer cell (LUT1 or FDRE) similar to the way "update_design -buffer_ports" operates in Vivado. This would help with integrating multiple designs...