Cindy Chen

clocking block with default clock skew macro

1

Verible Lint flagged a syntax error in the code below: ``` ../src/lowrisc_dv_jtag_agent_0.1/jtag_if.sv:29:19: syntax error, rejected "`JTAG_IF_HOST_CB_INPUT_SKEW" (syntax-error). ../src/lowrisc_dv_jtag_agent_0.1/jtag_if.sv:33:3: syntax error, rejected "endclocking" (syntax-error). ``` SystemVerilog code: ```systemverilog `ifndef JTAG_IF_HOST_CB_INPUT_SKEW `define...

[dv/pwm] Post V2S TODO list

7

Because all V2S requirements are met, I am going to move the remaining items to post V2: - [ ] pwm_env_pkg functional coverage is low.  - [ ] Check...

[chip-test] chip_sw_usb_suspend

5

### Test point name [chip_sw_usb_suspend](https://github.com/lowRISC/opentitan/blob/master/hw/top_earlgrey/data/chip_testplan.hjson#L288) ### Host side component SystemVerilog ### OpenTitanTool infrastructure implemented Unknown ### Contact person @a-will ### Checklist Please fill out this checklist as items are completed....