Christian Mardmöller

Simulation race condition in frontend.v

1

For the fifo definition hazard3_frontend.v uses the same signals in a synchronous process (e.g. in fifo_update for `fifo_mem[0..FIFO_DEPTH-1]`) and an asynchronous process (e.g. boundary_conditions for `fifo_mem[FIFO_DEPTH]`). From verilog language definition...

Incorrect arbitration in case of waits on a higher prior AHB

2

The arbitration fails if higher priority src interface overrules a lower priority src interface in two consecutive accesses. If the higher priority src interface has a single access, the old...